The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Jul. 31, 2015
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Gilberto Curatola, Villach, AT;

Martin Huber, Villach, AT;

Ingo Daumiller, Faak, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/26513 (2013.01); H01L 29/0619 (2013.01); H01L 29/0649 (2013.01); H01L 29/1075 (2013.01); H01L 29/1083 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/2003 (2013.01);
Abstract

A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.


Find Patent Forward Citations

Curatola, Gilberto. (2022). Breakdown resistant hemt substrate and device (U.S. Patent No. 11289593). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11289593

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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