The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Jul. 07, 2020
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Keishi Watanabe, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 23/00 (2006.01); H01L 27/08 (2006.01); H01L 29/866 (2006.01); H01L 27/02 (2006.01); H01L 27/07 (2006.01); H01L 29/40 (2006.01); H01L 29/861 (2006.01); H01L 29/66 (2006.01); H01L 29/868 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 24/05 (2013.01); H01L 27/0814 (2013.01); H01L 29/0607 (2013.01); H01L 29/866 (2013.01);
Abstract

The present invention provides a diode chip, including: a semiconductor chip, including a p-type first semiconductor layer and an n-type second semiconductor layer formed on the first semiconductor layer; a first pad separation trench, formed on the semiconductor chip in a manner of penetrating the second semiconductor layer till reaching the first semiconductor layer, and forming a first internal parasitic capacitance between the first semiconductor layer and the second semiconductor layer by separating a portion of the semiconductor chip from other regions; an inter-insulation layer, covering the second semiconductor layer; and a first electrode layer, being opposite to the region separated by the first pad separation trench with the inter-insulation layer interposed in between, and forming, between the first electrode layer and the semiconductor chip, a first external parasitic capacitance connected in series to the first internal parasitic capacitance.


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