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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11289525 B1

PDFFull Text
Date of Patent:
Mar. 29, 2022

Filed:

Mar. 11, 2016

Solid-state imaging device and electronic apparatus

Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Hajime Yamagishi, Kanagawa, JP;

Kiyotaka Tabuchi, Kanagawa, JP;

Masaki Okamoto, Kanagawa, JP;

Takashi Oinoue, Tokyo, JP;

Minoru Ishida, Tokyo, JP;

Shota Hida, Nagasaki, JP;

Kazutaka Yamane, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:

Chip Law Group

Primary Examiner:

Suberr L Chi

Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 27/14 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/552 (2006.01); H01L 23/48 (2006.01); H04N 5/357 (2011.01); H04N 5/365 (2011.01); H04N 5/376 (2011.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 23/5225 (2013.01); H01L 23/5286 (2013.01); H01L 23/552 (2013.01); H01L 27/14 (2013.01); H01L 27/146 (2013.01); H01L 27/14623 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H01L 23/481 (2013.01); H01L 27/14627 (2013.01); H04N 5/3575 (2013.01); H04N 5/365 (2013.01); H04N 5/378 (2013.01); H04N 5/3765 (2013.01);
Abstract

This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.

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