The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Dec. 09, 2020
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Wei-Yu Lin, Hsinchu, TW;

Shih-Hao Cheng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 21/04 (2006.01); H01L 21/324 (2006.01); H01L 21/761 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0251 (2013.01); H01L 29/1095 (2013.01); H01L 29/66734 (2013.01); H01L 29/7803 (2013.01); H01L 29/7813 (2013.01);
Abstract

A method of manufacturing a trench transistor structure including the following steps is provided. A substrate structure is provided. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. A transistor device is formed in the first region. The transistor device includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. An electrostatic discharge (ESD) protection device is formed in the second region. The ESD protection device includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.


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