The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Apr. 20, 2017
Applicant:

Palo Alto Research Center Incorporated, Palo Alto, CA (US);

Inventors:

Warren B. Jackson, San Francisco, CA (US);

Vanishree Rao, Mountain View, CA (US);

Eugene M. Chow, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); G06F 21/86 (2013.01); H01L 23/31 (2006.01); G06F 21/57 (2013.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H01L 24/72 (2013.01); G06F 21/57 (2013.01); G06F 21/86 (2013.01); H01L 23/3157 (2013.01); H04L 9/3234 (2013.01); H01L 2224/72 (2013.01); H01L 2924/0104 (2013.01); H01L 2924/01024 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01042 (2013.01); H04L 2209/127 (2013.01); H04L 2209/805 (2013.01); H04L 2209/88 (2013.01);
Abstract

A secured system includes at least one semiconductor chip comprising information processing circuitry. An array of contact pads is disposed on a surface of the chip and is electrically coupled to the information processing circuitry. The secured system includes one or more semiconductor chiplets. Each chiplet comprises at least a portion of at least one hardware trusted platform module that cryptographically secures the information processing circuitry. An array of electrically conductive microsprings is disposed on a surface of the chiplet and is electrically coupled between the hardware trusted platform module and the contact pads.


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