The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Feb. 20, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jaimal Mallory Williamson, McKinney, TX (US);

Snehamay Sinha, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/642 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/81815 (2013.01);
Abstract

A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.


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