The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Feb. 09, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Ran Zamir, Ramat Gan, IL;

Eran Sharon, Rishon Lezion, IL;

Idan Goldenberg, Ramat Hasharon, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/46 (2006.01); G11C 29/20 (2006.01); G11C 29/10 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/46 (2013.01); G11C 29/10 (2013.01); G11C 29/20 (2013.01); G11C 29/44 (2013.01);
Abstract

Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.


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