The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Oct. 03, 2020
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Andy Wangkun Chen, Austin, TX (US);

Yew Keong Chong, Austin, TX (US);

Tom Shore, Austin, TX (US);

Gus Yeung, Austin, TX (US);

Marlin Wayne Frederick, Jr., Austin, TX (US);

Sriram Thyagarajan, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
G06F 30/39 (2020.01); G06F 30/30 (2020.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01);
Abstract

Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.


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