The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Nov. 15, 2019
Applicant:

The Charles Stark Draper Laboratory, Inc., Cambridge, MA (US);

Inventors:

Nhut Tran, Natick, MA (US);

J. Ryan Prince, Stow, MA (US);

Brian Nugent, Acton, MA (US);

Elliot Greenwald, Cambridge, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/79 (2013.01); G06F 9/455 (2018.01); G06F 21/82 (2013.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
G06F 21/79 (2013.01); G06F 9/45508 (2013.01); G06F 21/602 (2013.01); G06F 21/82 (2013.01);
Abstract

An embodiment is directed to a hardware circuit for performing operations on data transmitted between a processor and memory. The hardware circuit includes a first interface communicatively coupled to the processor. The first interface configured to emulate a first protocol of the memory. The hardware circuit further includes a second interface communicatively coupled to the memory. The second interface configured to emulates a second protocol of the processor. The hardware circuit also includes hardware logic configured with a bi-directional path, such that each of the first and second interfaces is associated with a different direction of the bi-directional path. The bi-directional path is configured to execute an operation on data received at both the first interface and the second interface.


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