The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Sep. 30, 2020
Applicant:

National Tsing Hua University, Hsinchu, TW;

Inventors:

Shi-Yu Huang, Hsinchu, TW;

Wei-Hao Chen, Hsinchu, TW;

Chu-Chun Hsu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); H03L 7/08 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31709 (2013.01); H03K 3/037 (2013.01); H03L 7/08 (2013.01);
Abstract

An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal outputted by a phase-locked loop, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.


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