The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Apr. 06, 2021
Applicant:

Pixart Imaging Incorporation, Hsinchu, TW;

Inventors:

Boon-Eu Seow, Penang, MY;

Ping-Seng Lee, Penang, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); G06F 1/08 (2006.01); G06F 1/06 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); G06F 1/06 (2013.01); G06F 1/08 (2013.01); H03K 19/21 (2013.01);
Abstract

A non-overlapping clock generator generating an in-phase output clock signal and a reversed-phase output clock signal which are non-overlapped with each other, includes: a first and a second XOR gates, a first and a second load transistors, which are cross coupled, and includes: a first and a second delay circuits. The first delay circuit is coupled between the in-phase output clock signal and a control terminal of the first load transistor. The second delay circuit is coupled between the reversed-phase output clock signal and a control terminal of the second load transistor. Each of the XOR gates includes at least one pass transistor logic circuit configured to execute XOR logic operation and coupled to a first control voltage. A non-overlapping period is determined according to the first control voltage and/or a first delay period of the first delay circuit and a second delay period of the second delay circuit.


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