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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11282840 B1

PDFFull Text
Date of Patent:
Mar. 22, 2022

Filed:

Dec. 30, 2019

High density vertical thyristor memory cell array with improved isolation

Applicant:

Tc Lab, Inc., Gilroy, CA (US);

Inventors:

Harry Luan, Saratoga, CA (US);

Valery Axelrad, Woodside, CA (US);

Assignee:

Kilopass Technology, Inc., San Jose, CA (US);

Attorney:

Aka Chan LLP

Primary Examiner:

Ajay Arora

Assistant Examiner:

Gardner W S. Swan

Int. Cl.
CPC ...
H01L 27/102 (2006.01); H01L 21/8229 (2006.01); H01L 27/108 (2006.01); H01L 27/11512 (2017.01); G11C 15/04 (2006.01); H01L 29/66 (2006.01); G11C 11/39 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1027 (2013.01); G11C 11/39 (2013.01); G11C 15/04 (2013.01); H01L 21/8229 (2013.01); H01L 27/108 (2013.01); H01L 27/10823 (2013.01); H01L 27/10844 (2013.01); H01L 27/11512 (2013.01); H01L 29/66371 (2013.01); H01L 27/0817 (2013.01);
Abstract

Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

Find Patent Forward Citations

Luan, Harry. (2022). High density vertical thyristor memory cell array with improved isolation (U.S. Patent No. 11282840). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11282840

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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