The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Mar. 25, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Sung Lae Oh, Cheongju-si, KR;

Sang Hyun Sung, Cheongju-si, KR;

Kwang Hwi Park, Icheon-si, KR;

Je Hyun Choi, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01); H01L 21/66 (2006.01); G11C 16/30 (2006.01); G01R 31/319 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G01R 31/31924 (2013.01); G11C 16/30 (2013.01); H01L 22/32 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A semiconductor device includes a first chip, divided into a plurality of regions, including a plurality of first pads and a plurality of first test pads in each of the plurality of regions; and a second chip including a plurality of second pads corresponding to the plurality of first pads and a plurality of second test pads corresponding to the plurality of first test pads, and bonded onto the first chip such that the plurality of second pads are coupled to the plurality of first pads. The second chip includes a voltage generation circuit linked to the plurality of second pads, that provides a compensated voltage to the plurality of second pads for each of the plurality of regions, based on a voltage drop value for each region due to a contact resistance between the plurality of first test pads and the plurality of second test pads.


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