The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Oct. 21, 2020
Applicant:

Meta Platforms, Inc., Menlo Park, CA (US);

Inventor:

Narsing Krishna Vijayrao, Santa Clara, CA (US);

Assignee:

Meta Platforms, Inc., Menlo Park, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 1/3296 (2019.01); G06F 15/00 (2006.01); G06F 1/18 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 1/185 (2013.01); G06F 1/186 (2013.01); G06F 1/3296 (2013.01); G06F 13/385 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); G06F 15/00 (2013.01); G06F 2213/0032 (2013.01);
Abstract

An expansion card may include a printed circuit board and a hardware accelerator that is disposed on the printed circuit board. The hardware accelerator may include application-specific hardware circuitry designed to perform a computing task. The hardware accelerator may also offload a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task. The expansion card may further include an edge connector, disposed on the printed circuit board, that is dimensioned to be inserted into an expansion socket of the computing device. The edge connector may couple the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket. The edge socket may also include a pinout that is more compact than a pinout specification defined for the computing bus. Various other apparatuses, systems, and methods are also disclosed.


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