The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Oct. 22, 2019
Applicants:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Arun A. Nair, Santa Clara, CA (US);

Michael Estlick, Fort Collins, CO (US);

Erik Swanson, Fort Collins, CO (US);

Sneha V. Desai, Markham, CA;

Donglin Ji, Fort Collins, CO (US);

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI TECHNOLOGIES ULC, Markham, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/384 (2013.01); G06F 9/3867 (2013.01);
Abstract

A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.


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