The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2022
Filed:
May. 18, 2020
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Ati Technologies Ulc, Markham, CA;
Benjamin Tsien, Santa Clara, CA (US);
Michael J. Tresidder, Austin, TX (US);
Ivan Yanfeng Wang, Markham, CA;
Kevin M. Lepak, Austin, TX (US);
Ann Ling, Santa Clara, CA (US);
Richard M. Born, Fort Collins, CA (US);
John P. Petry, Santa Clara, CA (US);
Bryan P. Broussard, Austin, TX (US);
Eric Christopher Morton, Austin, TX (US);
Advanced Micro Devices, Inc., Santa Clara, CA (US);
ATI Technologies ULC, Markham, CA;
Abstract
Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.