The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Feb. 25, 2020
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Yuki Watanabe, Funabashi Chiba, JP;

Masato Nakazato, Kawasaki Kanagawa, JP;

Shohei Morishima, Kawasaki Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 11/263 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31703 (2013.01); G01R 31/31724 (2013.01); G01R 31/318547 (2013.01); G01R 31/318566 (2013.01); G06F 11/263 (2013.01);
Abstract

According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.


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