The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Oct. 01, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byung-guk Seo, Hwaseong-si, KR;

Sun-ki Yun, Yongin-si, KR;

Su-jin Kim, Hwaseong-si, KR;

Hwi-jong Yoo, Seoul, KR;

Young-rok Oh, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); G11C 5/04 (2006.01); H05K 1/11 (2006.01); G06F 13/16 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); G06F 13/1668 (2013.01); G06F 13/1673 (2013.01); G11C 5/04 (2013.01); H05K 1/115 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10545 (2013.01); H05K 2201/10734 (2013.01);
Abstract

A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2(where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.


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