The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Apr. 16, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sai Aditya Krishnaswamy Nurani, Hyderabad, IN;

Joseph Palackal Mathew, Podimattom, IN;

Prasanth K, Ottapalam, IN;

Visvesvaraya Appala Pentakota, Bengaluru, IN;

Shagun Dusad, Bengaluru, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1245 (2013.01); G11C 27/02 (2013.01); H03M 1/121 (2013.01);
Abstract

A sample-and-hold circuit includes a first input resistor, a first transistor, a first capacitor, a second resistor, and a first current source device. A first current terminal of the first transistor is coupled to the first input resistor. A first terminal of the first capacitor is coupled to the second current terminal of the first transistor at a first output node. A first terminal of the second resistor is coupled to the second terminal of the first transistor at the first output node. The first current source device is coupled the first input resistor and to the first current terminal of the first transistor.


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