The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Aug. 26, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Junya Matsuno, Yokohama Kanagawa, JP;

Kensuke Yamamoto, Yokohama Kanagawa, JP;

Ryo Fukuda, Yokohama Kanagawa, JP;

Masaru Koyanagi, Ota Tokyo, JP;

Kenro Kubota, Fujisawa Kanagawa, JP;

Masato Dome, Yokohama Kanagawa, JP;

Assignee:

KlOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 7/06 (2006.01); H03K 19/0185 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); H03K 19/018571 (2013.01); G11C 7/065 (2013.01); G11C 7/1087 (2013.01); G11C 11/419 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.


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