The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Dec. 23, 2019
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Christelle Charpin-Nicolle, Grenoble, FR;

Sophie Bernasconi, Grenoble, FR;

Aomar Halimaoui, Grenoble, FR;

Florian Pebay-Peyroula, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 29/40 (2006.01); H01L 23/00 (2006.01); H01L 21/74 (2006.01); H01L 27/24 (2006.01); H01L 23/522 (2006.01); H01L 23/544 (2006.01); H04L 9/32 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/573 (2013.01); H01L 21/743 (2013.01); H01L 23/5226 (2013.01); H01L 23/544 (2013.01); H01L 27/2463 (2013.01); H04L 9/3278 (2013.01); H01L 23/5283 (2013.01);
Abstract

A method for securing an integrated circuit upon making it includes the steps of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.


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