The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2022
Filed:
Apr. 30, 2020
Amazon Technologies, Inc., Seattle, WA (US);
Mark Bradley Davis, Austin, TX (US);
Erez Izenberg, Tel Aviv, IL;
Robert Michael Johnson, Austin, TX (US);
Asif Khan, Austin, TX (US);
Islam Mohamed Hatem Abdulfattah Mohamed Atta, Vancouver, CA;
Nafea Bshara, San Jose, CA (US);
Christopher Joseph Pettey, Woodinville, WA (US);
Amazon Technologies, Inc., Seattle, WA (US);
Abstract
Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.