The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Mar. 07, 2018
Applicant:

Sri International, Menlo Park, CA (US);

Inventors:

Richard Sita, Audubon, NJ (US);

Michael G. Kane, Princeton, NJ (US);

Assignee:

SRI International, Menlo Park, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); G01R 31/2822 (2013.01); H01L 21/78 (2013.01); H01L 22/14 (2013.01); H01L 22/32 (2013.01);
Abstract

Manufacturing integrated circuits is discussed with steps as follows. Creating a wafer with a plurality of dies, where each die contains its own integrated circuit. Fabricating multiple instances of TAP circuitry located in a margin between dies of the wafer. Fabricating on the wafer one row of test pads and power pads per group of dies on the wafer, where the row of test pads and power pads is electrically connected and shared among all of the dies in the group. The test and power pads connect to a chain of TAP circuitry in order to supply operating power as well as testing data to verify the integrity of each die in that group of dies. Singulating the dies to create each instance of the integrated circuit, and during the singulation process, the TAP circuitry located in the margin between the dies is destroyed.


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