The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2022
Filed:
May. 14, 2021
Applicant:
Massachusetts Institute of Technology, Cambridge, MA (US);
Inventors:
Christian Lau, Boston, MA (US);
Max Shulaker, Weston, MA (US);
Assignee:
Massachusetts Institute of Technology, Cambridge, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/00 (2006.01); H01L 51/05 (2006.01); C01B 32/174 (2017.01); H01L 51/10 (2006.01); H01L 27/28 (2006.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 51/0025 (2013.01); C01B 32/174 (2017.08); H01L 51/0048 (2013.01); H01L 51/0558 (2013.01); H01L 51/107 (2013.01); B82Y 40/00 (2013.01); C01B 2202/22 (2013.01); C01P 2004/13 (2013.01); C01P 2004/64 (2013.01); H01L 27/283 (2013.01);
Abstract
A technology called RINSE (Removal of Incubated Nanotubes through Selective Exfoliation) is demonstrated. RINSE removes carbon nanotube (CNT) aggregates in CNFETs without compromising CNFET performance. In RINSE, CNTs are deposited on a substrate, coated with a thin adhesive layer, and sonicated. The adhesive layer is strong enough to keep the individual CNTs on the substrate, but not the larger CNT aggregates. When combined with a CNFET CMOS process as disclosed here, record CNFET CMOS yield and uniformity can be realized.