The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

May. 15, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventor:

Kenichi Murooka, San Jose, CA (US);

Assignee:

KIOXIA CORPORATION, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); G11C 8/10 (2013.01); G11C 13/0002 (2013.01); G11C 13/0023 (2013.01); H01L 27/249 (2013.01); H01L 27/2463 (2013.01); H01L 45/04 (2013.01); H01L 45/1226 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 45/149 (2013.01); H01L 45/1608 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01);
Abstract

A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M<2×N×k is satisfied.


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