The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Nov. 30, 2018
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Hiroyuki Kawashima, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 21/7682 (2013.01); H01L 21/76804 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 27/14634 (2013.01);
Abstract

To reduce the capacitance between wiring lines of a semiconductor device, while maintaining mechanical strength and reliability. A semiconductor device including: a multilayer wiring layer in which a plurality of interlayer films and a plurality of diffusion preventing films are alternately stacked, and a wiring line is formed in the interlayer films; a contact via that penetrates a via insulating layer formed on one surface of the multilayer wiring layer, and is electrically connected to the wiring line of the multilayer wiring layer; a through hole that penetrates at least one of the interlayer films and the diffusion preventing films from the other surface of the multilayer wiring layer on the opposite side from the one surface; and an air gap that is connected to the through hole, and is formed in at least one of the interlayer films, to expose the contact via.


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