The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Jun. 01, 2020
Applicant:

Alibaba Group Holding Limited, Grand Cayman, KY;

Inventor:

Wei Han, San Mateo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 21/8232 (2006.01); H01L 23/48 (2006.01); H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/8232 (2013.01); H01L 23/481 (2013.01); H01L 21/302 (2013.01);
Abstract

The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.


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