Memory device with improved bit line precharge performance and method of operating the memory device

Abstract

Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array, a plurality of page buffer groups, and a program operation controller. The memory cell array may include a plurality of memory cells. The page buffer groups may be coupled to the plurality of memory cells through a plurality of bit line groups, and may be configured to perform bit line precharge operations on the plurality of bit line groups. The program operation controller may be configured to control the plurality of page buffer groups to perform the bit line precharge operations initiated at different time points during a program operation on the plurality of memory cells, and to adjust an interval between initiation time points of the bit line precharge operations depending on a progress of the program operation.