The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11270051 B1

Date of Patent:

Mar. 08, 2022

Filed:

Nov. 09, 2020

Model-based design and partitioning for heterogeneous integrated circuits

Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Avinash Somalinga Suresh, Hyderabad, IN;

Ali Behboodian, Fremont, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:

Kevin T. Cuenot

Primary Examiner:

Naum Levin

Int. Cl.

CPC ...

G06F 30/00 (2020.01); G06F 30/327 (2020.01); G06F 30/398 (2020.01); G06F 30/3953 (2020.01); G06F 30/392 (2020.01);

U.S. Cl.

CPC ...

G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/3953 (2020.01);

Abstract

Model-based implementation of a design for a heterogeneous integrated circuit can include converting a model, created as a data structure using a modeling system, into a data flow graph, wherein the model represents a design for implementation in an integrated circuit having a plurality of systems, the systems being heterogeneous, classifying nodes of the data flow graph for implementation in different ones of the plurality of systems of the integrated circuit, and partitioning the data flow graph into a plurality of sub-graphs based on the classifying, wherein each sub-graph corresponds to a different one of the plurality of systems. From each sub-graph, a portion of high-level language (HLL) program code can be generated. Each portion of HLL program code may be specific to the system corresponding to the sub-graph from which the portion of HLL program code was generated.

Find Patent Forward Citations

Suresh, Avinash. (2022). Model-based design and partitioning for heterogeneous integrated circuits (U.S. Patent No. 11270051). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11270051

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile