The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Apr. 29, 2020
Applicant:

Drexel University, Philadelphia, PA (US);

Inventors:

Ioannis Savidis, Wallingford, PA (US);

Vaibhav Venugopal Rao, Philadelphia, PA (US);

Kyle Joseph Juretus, Quakertown, PA (US);

Assignee:

Drexel University, Philadelphia, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/75 (2013.01); H03K 21/02 (2006.01); H03K 5/1532 (2006.01); H03M 1/36 (2006.01);
U.S. Cl.
CPC ...
G06F 21/75 (2013.01); H03K 5/1532 (2013.01); H03K 21/02 (2013.01); H03M 1/365 (2013.01);
Abstract

The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3× increase in the number of iterations required to complete the SAT attack.


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