The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Feb. 13, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Gregory Michael Wright, Chapel Hill, NC (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 12/0813 (2016.01); G06F 12/0864 (2016.01); G06F 12/1009 (2016.01); G06F 12/0842 (2016.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3806 (2013.01); G06F 9/30189 (2013.01); G06F 9/3842 (2013.01); G06F 9/3861 (2013.01); G06F 12/0223 (2013.01); G06F 12/06 (2013.01); G06F 12/0813 (2013.01); G06F 12/0842 (2013.01); G06F 12/0864 (2013.01); G06F 12/1009 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/7201 (2013.01);
Abstract

The disclosure relates to processing in-flight blocks in a processor pipeline according to an expected execution mode to reduce synchronization delays that could otherwise arise due to transitions among processor modes with varying privilege levels (e.g., user mode, supervisor mode, hypervisor mode, etc.). More particularly, a program counter associated with an instruction block to be fetched may be translated to one or more execute permissions associated with the instruction block and the instruction block may be associated with a speculative execution mode based at least in part on the one or more execute permissions. Accordingly, the instruction block may be processed relative to the speculative execution mode while in-flight within the processor pipeline.


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