The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Apr. 21, 2017
Applicant:

Hewlett-packard Development Company, L.p., Spring, TX (US);

Inventors:

Dominique Gougeon, Vancouver, WA (US);

Frankie Alcazar, Vancouver, WA (US);

Paul D Bliley, Vancouver, WA (US);

Tyler Kapp, Vancouver, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3287 (2019.01); G06F 1/3234 (2019.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3253 (2013.01); G06F 1/3275 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Reducing power consumption of an electrical device is provided. The electrical device includes a first and a second module. The first and second modules include a first and a second memory, and a first and second system on chip (SoC) respectively. The first and second SoCs include a first and a second micro-processor respectively. A PCI-e bus connects the modules. The second module enters a sleep mode state that includes a first and a second sleep mode. The second module transitions between the first and second sleep modes while in the sleep mode state. The second SoC reduces a power state of the second module during the first sleep mode, and powers off the second SoC during the second sleep mode.


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