The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Jan. 28, 2020
Applicant:

GE Precision Healthcare Llc, Milwaukee, WI (US);

Inventors:

Stephane Vandroux, Paris, FR;

Gauthier Libaux, Versailles, FR;

Assignee:

GE Precision Healthcare LLC, Milwaukee, WI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05G 1/08 (2006.01); A61B 6/00 (2006.01); G06F 30/34 (2020.01); H03K 19/0175 (2006.01); H03K 3/0233 (2006.01); A61B 6/04 (2006.01);
U.S. Cl.
CPC ...
A61B 6/548 (2013.01); A61B 6/0487 (2020.08); A61B 6/42 (2013.01); A61B 6/4441 (2013.01); A61B 6/4452 (2013.01); A61B 6/461 (2013.01); A61B 6/467 (2013.01); A61B 6/586 (2013.01); G06F 30/34 (2020.01); H03K 3/02337 (2013.01); H03K 19/017581 (2013.01);
Abstract

In one example, an electronic system includes, a user interface comprising an input device, a first actuator and a second actuator, the first and second actuators dually actuated by the input device, and a controller, including a comparator, a programmable device, and executable instructions residing in non-transitory memory thereon to, receive first and second output signals from the first and second actuators, respectively, convert the first and second output signals to first and second real-time logic states at the comparator, input the first and second real-time logic states from the comparator to the programmable device, and determine a fault status of the first and second actuators based on the first and second logic states input to a state machine of the programmable device, wherein the first and second logic states input to the state machine include the real-time logic states and historical logic states stored at the controller.


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