The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Sep. 25, 2019
Applicant:

The Regents of the University of California, Oakland, CA (US);

Inventors:

Roberto Proietti, Davis, CA (US);

Sung-Joo Ben Yoo, Davis, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04Q 11/00 (2006.01); H04J 14/02 (2006.01);
U.S. Cl.
CPC ...
H04Q 11/0005 (2013.01); H04J 14/0212 (2013.01); H04Q 11/0066 (2013.01); H04Q 2011/0032 (2013.01);
Abstract

The disclosed system implements a bandwidth-reconfigurable optical interconnect, which couples optical signals between N interconnect inputs and N interconnect outputs. The system includes an arrayed waveguide grating router (AWGR), which provides cyclic, single-wavelength, all-to-all routing between N AWGR inputs and N AWGR outputs. The system also includes a wavelength-insensitive switch, which provides all-wavelength, all-to-all connectivity between N wavelength-insensitive inputs and N wavelength-insensitive outputs. The system additionally includes a wavelength-selective input switch, which selectively directs up to L wavelengths from each of the N interconnect inputs into a corresponding input of the wavelength-insensitive switch, wherein unselected wavelengths from each of the N interconnect inputs pass into a corresponding AWGR input. Finally, the system includes a wavelength-selective output switch, which selectively directs up to L wavelengths from each of the N wavelength-insensitive outputs into a corresponding interconnect output, wherein each of the N AWGR outputs pass into a corresponding interconnect output.


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