The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Dec. 02, 2020
Applicant:

National University of Defense Technology, Hunan, CN;

Inventors:

Mingche Lai, Hunan, CN;

Liquan Xiao, Hunan, CN;

Junsheng Chang, Hunan, CN;

Pingjing Lu, Hunan, CN;

Zhengbin Pang, Hunan, CN;

Canwen Xiao, Hunan, CN;

Lu Liu, Hunan, CN;

Jijun Cao, Hunan, CN;

Yi Dai, Hunan, CN;

Jiaqing Xu, Hunan, CN;

Qiang Wang, Hunan, CN;

Fangxu Lv, Hunan, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 1/00 (2006.01); H04L 12/46 (2006.01); H04L 25/03 (2006.01); H04L 69/24 (2022.01);
U.S. Cl.
CPC ...
H04L 69/24 (2013.01); H04L 1/0042 (2013.01); H04L 12/46 (2013.01); H04L 25/03159 (2013.01); H04L 2025/03815 (2013.01);
Abstract

This invention discloses a multimode interconnection interface controller for a converged network, which comprises a SERDES element responsible for serial/parallel conversion, a LANE_TXCLK element responsible for generating a transmit clock, a SERDES initialization element responsible for link training and rate negotiation, and a PCS_EB coding element and an PCS_AF coding element responsible for physical layer coding of messages. The link training and rate negotiation are completed automatically via the shared SERDES initialization element. More universality and flexibility are provided for interconnection chip design by the PCS_EB coding element. The PCS_AF coding element is provided to reduce message penetration delay. The multimode interconnection interface controller is integrated in a single chip. Through flexible configuration, the single chip can meet transmission requirements of dedicated high speed networks and Ethernet networks. The multimode interconnection interface controller also supports interconnection of data center Ethernet and high performance computing high speed network.


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