The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Mar. 24, 2020
Applicant:

Marvell Asia Pte, Ltd., Singapore, SG;

Inventors:

Andre Szczepanek, Santa Clara, CA (US);

Arash Farhoodfar, Santa Clara, CA (US);

Sudeep Bhoja, San Jose, CA (US);

Sean Batty, Machynlleth, GB;

Shaun Lytollis, Santa Clara, CA (US);

Assignee:

Marvell Asia Pte, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/01 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
H03M 13/015 (2013.01); H03M 13/158 (2013.01); H03M 13/1515 (2013.01);
Abstract

Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GFReed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).


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