The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Jan. 29, 2021
Applicant:

Seagate Technology Llc, Fremont, CA (US);

Inventors:

Jason Bellorado, San Jose, CA (US);

Marcus Marrow, San Jose, CA (US);

Zheng Wu, Los Altos, CA (US);

Assignee:

Seagate Technology LLC, Fremont, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11B 20/10 (2006.01); G11B 5/00 (2006.01); H03M 1/06 (2006.01); H03G 3/30 (2006.01); G11B 5/027 (2006.01); G11B 5/012 (2006.01);
U.S. Cl.
CPC ...
H03M 1/06 (2013.01); G11B 5/012 (2013.01); G11B 5/027 (2013.01); G11B 20/10324 (2013.01); H03G 3/30 (2013.01); H03G 2201/103 (2013.01);
Abstract

Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.


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