The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Dec. 18, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chan-sic Yoon, Anyang-si, KR;

Ho-in Lee, Suwon-si, KR;

Ki-seok Lee, Hwaseong-si, KR;

Je-min Park, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11573 (2017.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 27/108 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76232 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); G11C 11/4085 (2013.01); H01L 27/10814 (2013.01);
Abstract

An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.


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