The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Aug. 01, 2019
Applicant:

Corning Incorporated, Corning, NY (US);

Inventors:

Ming-Huang Huang, Ithaca, NY (US);

Hoon Kim, Horseheads, NY (US);

Xu Ouyang, Painted Post, NY (US);

Assignee:

Corning Incorporated, Corning, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); B81B 7/00 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3142 (2013.01); B81B 7/0041 (2013.01); H01L 21/0228 (2013.01); H01L 21/02422 (2013.01); H01L 21/56 (2013.01); H01L 21/76871 (2013.01); H01L 23/3121 (2013.01); H01L 23/49838 (2013.01);
Abstract

An electrical component package includes a glass substrate, an interposer panel positioned on the glass substrate, the interposer panel comprising a device cavity, a wafer positioned on the interposer panel such that the device cavity is enclosed by the glass substrate, the interposer panel, and the wafer. The electrical component package further includes a metal seed layer disposed between the interposer panel and the wafer, and a dielectric coating. The dielectric coating hermetically seals the interposer panel to the glass substrate, the interposer panel to the metal seed layer and the wafer, and the interposer panel hermetically seals the metal seed layer to the glass substrate such that the device cavity is hermetically sealed from ambient atmosphere.


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