The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Nov. 29, 2018
Applicant:

Wavepia Co., Ltd., Gyeonggi-do, KR;

Inventors:

Sang-Hun Lee, Gyeonggi-do, KR;

Kue-Jin Han, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/66 (2006.01); H03F 3/195 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4839 (2013.01); H01L 21/4828 (2013.01); H01L 23/49861 (2013.01); H01L 23/66 (2013.01); H03F 3/195 (2013.01); H01L 2223/6655 (2013.01);
Abstract

A method of manufacturing a power amplifier package embedded with an input-output circuit including a dielectric circuit board, a heat sink and lead frames, the method comprising: the step of preparing the dielectric circuit board including the steps of forming a power amplifier hole in which a power amplifier chip is to be disposed on a dielectric substrate, printing an input matching network metal pattern on a left side of the power amplifier hole, and printing an output matching network metal pattern on a right side of the power amplifier hole, and sintering the input matching network metal pattern and the output matching network metal pattern printed on the dielectric substrate; the step of preparing the lead frames by etching alloy 42 and plating nickel; and the step of attaching the heat sink on a bottom surface of the dielectric circuit board.


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