The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Mar. 31, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Amitava Majumdar, San Jose, CA (US);

Albert Shih-Huai Lin, Mountain View, CA (US);

Partho Tapan Chaudhuri, Nagpur, IN;

Niravkumar Patel, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/3308 (2020.01); G06F 30/398 (2020.01); G06F 11/00 (2006.01); G01R 31/28 (2006.01); H01L 25/00 (2006.01); H03K 19/00 (2006.01); G06F 115/08 (2020.01); G06F 11/08 (2006.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G01R 31/28 (2013.01); G06F 11/08 (2013.01); G06F 30/3308 (2020.01); G06F 30/398 (2020.01); G06F 2115/08 (2020.01); H01L 25/00 (2013.01); H03K 19/00 (2013.01);
Abstract

A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.


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