The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Nov. 16, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ian Andrew Swarbrick, Santa Clara, CA (US);

Sagheer Ahmad, Cupertino, CA (US);

Ygal Arbel, Morgan Hill, CA (US);

Dinesh Gaitonde, Fremont, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 7/50 (2006.01); G06F 15/78 (2006.01); H04L 41/0813 (2022.01); H04L 49/109 (2022.01); G06F 13/42 (2006.01); H04L 12/40 (2006.01); H04L 45/42 (2022.01); H04L 45/60 (2022.01);
U.S. Cl.
CPC ...
G06F 15/7825 (2013.01); G06F 13/4226 (2013.01); G06F 15/7867 (2013.01); H04L 12/40019 (2013.01); H04L 41/0813 (2013.01); H04L 45/42 (2013.01); H04L 45/60 (2013.01); H04L 49/109 (2013.01); G06F 2213/0038 (2013.01);
Abstract

An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.


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