The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Dec. 29, 2020
Applicant:

Tata Consultancy Services Limited, Mumbai, IN;

Inventors:

Mahesh Damodar Barve, Pune, IN;

Sunil Puranik, Pune, IN;

Swapnil Rodi, Thane West, IN;

Manoj Nambiar, Thane West, IN;

Dhaval Shah, Thane West, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01); H03K 19/17728 (2020.01); G06F 9/54 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4221 (2013.01); G06F 9/546 (2013.01); G06F 13/4022 (2013.01); H03K 19/17728 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.


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