The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Jan. 16, 2020
Applicant:

Graphcore Limited, Bristol, GB;

Inventors:

Simon Christian Knowles, Corston, GB;

Daniel John Pelham Wilkinson, West Harptree, GB;

Richard Luke Southwell Osborne, Bristol, GB;

Alan Graham Alexander, Wotton-Under-Edge, GB;

Stephen Felix, Bristol, GB;

Jonathan Mangnall, Portishead, GB;

David Lacey, Cheltenham, GB;

Assignee:

GRAPHCORE LIMITED, Bristol, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 9/52 (2006.01); G06F 9/30 (2018.01); G06F 9/54 (2006.01); G06F 9/38 (2018.01); G06F 15/173 (2006.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 9/3009 (2013.01); G06F 9/30087 (2013.01); G06F 9/30145 (2013.01); G06F 9/3851 (2013.01); G06F 9/52 (2013.01); G06F 9/54 (2013.01); G06F 15/17325 (2013.01); G06N 20/00 (2019.01);
Abstract

The invention relates to a computer implemented method of generating multiple programs to deliver a computerised function, each program to be executed in a processing unit of a computer comprising a plurality of processing units each having instruction storage for holding a local program, an execution unit for executing the local program and data storage for holding data, a switching fabric connected to an output interface of each processing unit and connectable to an input interface of each processing unit by switching circuitry controllable by each processing unit, and a synchronisation module operable to generate a synchronisation signal, the method comprising: generating a local program for each processing unit comprising a sequence of executable instructions; determining for each processing unit a relative time of execution of instructions of each local program whereby a local program allocated to one processing unit is scheduled to execute with a predetermined delay relative to a synchronisation signal a send instruction to transmit at least one data packet at a predetermined transmit time, relative to the synchronisation signal, destined for a recipient processing unit but having no destination identifier, and a local program allocated to the recipient processing unit is scheduled to execute at a predetermined switch time a switch control instruction to control the switching circuitry to connect its processing unit wire to the switching fabric to receive the data packet at a receive time.


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