Methods and apparatus for multi-lane mapping, link training and lower power modes for a high speed bus interface

Abstract

Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.