The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Jan. 17, 2020
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Rishi Kanth Alapati, Dublin, CA (US);

Parasuramji Rajendran, San Jose, CA (US);

Weiming Xu, Palo Alto, CA (US);

Shireesh Kumar Singh, Sunnyvale, CA (US);

Aditi Vutukuri, Milpitas, CA (US);

Anuprem Chalvadi, Milpitas, CA (US);

Chidambareswaran Raman, Sunnyvale, CA (US);

Margaret Angeline Petrus, San Jose, CA (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 12/24 (2006.01); H04L 29/12 (2006.01); H04L 41/0806 (2022.01); H04L 41/00 (2022.01); H04L 61/5007 (2022.01);
U.S. Cl.
CPC ...
H04L 63/0236 (2013.01); H04L 41/0806 (2013.01); H04L 41/20 (2013.01); H04L 61/2007 (2013.01);
Abstract

Described herein are systems and methods to manage blacklists and duplicate addresses in software defined networks (SDNs). In one implementation, a method includes, in a control plane and data plane of an SDN environment, obtaining a blacklist for a logical port in the SDN environment. The method further includes deleting realized address bindings in a realized address list for the logical port that match the one or more address bindings in the blacklist and preventing subsequent address bindings that match the one or more address bindings in the blacklist from being added to the realized address list.


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