The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Aug. 21, 2020
Applicant:

Pensando Systems Inc., Milpitas, CA (US);

Inventors:

Ajeer Salil Pudiyapura, Sunnyvale, CA (US);

Sarat Babu Kamisetty, Fremont, CA (US);

Krishna Doddapaneni, Cupertino, CA (US);

Assignee:

PENSANDO SYSTEMS INC., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/66 (2006.01); H04L 45/745 (2022.01); H04L 45/748 (2022.01); H04L 45/48 (2022.01); H04L 49/90 (2022.01); H04L 45/74 (2022.01); H04L 49/901 (2022.01); H04L 47/2441 (2022.01);
U.S. Cl.
CPC ...
H04L 45/7457 (2013.01); H04L 45/48 (2013.01); H04L 45/742 (2013.01); H04L 45/748 (2013.01); H04L 47/2441 (2013.01); H04L 49/901 (2013.01); H04L 49/9068 (2013.01);
Abstract

Described are programmable IO devices configured to perform operations. These operations comprise: determining a set of range-based elements for a network; sorting the set of range-based elements according to a global order among the range-based elements; generating an interval table from the sorted range-based elements; generating an interval binary search tree from the interval table; propagating data stored in subtrees of interior stages of the interval binary search tree to subtrees of a last stage of the interval binary search tree such that the interior stages do not comprise data; converting the interval binary search tree to a Pensando Tree; compressing multiple levels of the Pensando Tree into cache-lines; and assembling the cache-lines in the memory unit such that each stage can compute an address of a next-cache line to be fetched by a next stage.


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