Latch architecture

Abstract

Disclosed is a latch architecture comprising an input circuit receiving input data and; a combinational network providing first intermediate data, first intermediate control signal and second intermediate control signal, based on latched input data from the input circuit; one or more first latches providing latched first intermediate data; a second latch providing a latched first intermediate control signal; a third latch providing a latched second intermediate control signal; and at least one fourth latch providing the output data; a decoder connected to the first latch and receiving the latched first intermediate data and providing second intermediate data. The at least one fourth latch receives input signals modified based on the latched first intermediate control signal, the latched second intermediate control signal and the second intermediate data. The first to third latches operate at an inverted clock signal and the at least one fourth latch operates at a non-inverted clock signal.