The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Dec. 17, 2020
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Péter Onódy, Budapest, HU;

András V. Horváth, Budapest, HU;

Assignee:

Skyworks Solutions, Inc., Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/125 (2006.01); H03K 5/1252 (2006.01); H03H 11/06 (2006.01); H03H 11/26 (2006.01); H03K 3/012 (2006.01); H03K 17/687 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 17/6872 (2013.01); H03K 17/6874 (2013.01); H03K 19/20 (2013.01);
Abstract

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.


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