The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Jul. 15, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Justin Philpott, San Francisco, CA (US);

Xiaocheng Jing, San Jose, CA (US);

Jingxue Lu, San Diego, CA (US);

Iulian Mirea, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H03F 1/30 (2006.01); H04B 1/04 (2006.01); H04B 1/16 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03F 1/305 (2013.01); H04B 1/04 (2013.01); H04B 1/1615 (2013.01); H03F 1/0211 (2013.01); H03F 1/0244 (2013.01); H03F 2200/411 (2013.01); H04B 2001/0408 (2013.01);
Abstract

Aspects of the present disclosure provide a high voltage switch with a fast turn-off. An example power supply circuit generally includes a capacitive element for coupling to a power terminal of an amplifier, a first switch configured to be closed in a first mode and to be open in a second mode, a second switch coupled in series between the first switch and the capacitive element and configured to be closed in the first mode and to be open in the second mode, a first circuit coupled to the first switch and configured to charge the capacitive element and power the amplifier in the first mode, and a buffer circuit having an output coupled to a first node and configured to output a first voltage level greater than half of a second voltage level at a second node.


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